This invention relates to an arrangement for recording an information signal on a magnetic record carrier, comprising a write head for recording information on the record carrier, and a write amplifier for driving the write head in response to the information signal, the write amplifier comprising:
a first write terminal, and a second write terminal, which are coupled to the write head; PA1 a first supply terminal and a second supply terminal for the connection of a supply voltage for the write amplifier; PA1 a first current mirror having a first current input terminal, a first current output terminal coupled to the first write terminal, and a first common current terminal connected to the first supply terminal; PA1 a second current mirror having a second current input terminal, a second current output terminal coupled to the second write terminal, and a second common current terminal connected to the first supply terminal; and PA1 current switching means for establishing a current path between the first current output terminal and the second supply terminal via the first write terminal and the second write terminal for a first value of the information signal and for establishing a current path between the second current output terminal and the second supply terminal via the first write terminal and the second write terminal for a second value of the information signal. PA1 a third current mirror having a third current input terminal, a third current output terminal coupled to the first write terminal, and a third common current terminal connected to the second supply terminal; PA1 a fourth current mirror having a fourth current input terminal, a fourth current output terminal coupled to the second write terminal, and a fourth common current terminal connected to the second supply terminal; PA1 a first switchable current source connected between the first current input terminal and the fourth current input terminal for supplying a first current for a first value of the information signal; and PA1 a second switchable current source connected between the second current input terminal and the third current input terminal for supplying a second current for the second value of the information signal. PA1 a first resistor connected between the first write terminal and a first node, a second resistor connected between the first node and the second write terminal, a third resistor connected between the first write terminal and a second node, a fourth resistor connected between the second node and the second write terminal, PA1 a first transistor of a first conductivity type having a control electrode, a first main electrode connected to the first node and a second main electrode coupled to the first supply terminal, PA1 a second transistor of the first conductivity type having a control electrode connected to the control electrode of the first transistor, a first main electrode, and a second main electrode connected to the control electrode of the second transistor, a fifth resistor connected between the first supply terminal and the second main electrode of the second transistor, PA1 a third transistor of the first conductivity type having a control electrode connected to the control electrode of the first transistor, a first main electrode connected to the first node and a second main electrode coupled to the second supply terminal, PA1 a fourth transistor of a second conductivity type having a control electrode, a first main electrode connected to the first node and a second main electrode coupled to one of the third current input terminal and the fourth current input terminal, a fifth transistor of the second conductivity type having a control electrode connected to the control electrode of the fourth transistor, a first main electrode connected to the first main electrode of the second transistor and a second main electrode connected to the control electrode of the fifth transistor, a sixth resistor connected between the second supply terminal and the second main electrode of the fifth transistor, PA1 a sixth transistor of the second conductivity type having a control electrode connected to the control electrode of the fourth transistor, a first main electrode connected to the second node and a second main electrode coupled to the other one of the third current the quiescent current input terminal and the fourth current input terminal. PA1 a seventh transistor of a first conductivity type having a control electrode connected to a third node, a first main electrode, and a second main electrode coupled to the first current input terminal, PA1 an eighth transistor of the first conductivity type having a control electrode connected to the control electrode of the seventh transistor, a first main electrode, and a second main electrode coupled to the first supply terminal, PA1 a ninth transistor of a second conductivity type having a control electrode connected to a fourth node, a first main electrode connected to the first main electrode of the seventh transistor, and a second main electrode coupled to the fourth current input terminal, a diode-connected tenth transistor of the second conductivity type having a first main electrode connected to the first main electrode of the eighth transistor and having a control electrode and second main electrode connected to the fourth node, PA1 a bias current source coupled to the fourth node to supply a bias current to the fourth node, PA1 an eleventh transistor of the first conductivity type having a control electrode connected to a fifth node, a first main electrode, and a second main electrode coupled to the second current input terminal, PA1 a twelfth transistor of the first conductivity type having a control electrode connected to the control electrode of the eleventh transistor, a first main electrode, and a second main electrode coupled to the first supply terminal, and a thirteenth transistor of the second conductivity type having a control electrode connected to the fourth node, a first main electrode connected to the first main electrode of the transistor, and a second main electrode coupled to the third current input terminal. PA1 a fourteenth transistor of the first conductivity type having a control electrode for receiving the information signal, a first main electrode connected to the third node and a second main electrode coupled to the first supply terminal, PA1 a fifteenth transistor of the first conductivity type having a control electrode for receiving the information signal, a first main electrode connected to the fifth node and a second main electrode coupled to the first supply terminal, PA1 a sixteenth transistor of the first conductivity type having a control electrode connected to the control electrode of the eighth transistor, a first main electrode connected to the first main electrode of the eighth transistor, and a second main electrode coupled to the fifth node, a seventeenth transistor of the first conductivity type having a control electrode connected to the control electrode of the twelfth transistor, a first main electrode connected to the first main electrode of the twelfth transistor, and a second main electrode coupled to the third node, the second main electrode of the eighth transistor being connected to the third node and the second main electrode of the twelfth transistor being connected to the fifth node.
The invention also relates to a write amplifier for use in such an arrangement.
Such an arrangement and write amplifier are known from U.S. Pat. No. 5,282,094, FIG. 1. Write amplifiers having inductive write heads are used, inter alia, in hard disk drives for the storage of digital information signals, the polarity of the write current through the write head being reversed in response to the bit pattern of the information signal. In the known arrangement polarity reversal is effected with current switching means which establish a low-impedance connection between one of the write terminals and the second supply terminal. The other write terminal is then connected to the high-impedance current output terminal of the first or the second current mirror. As a result, the common-mode voltage across the write head does not have a fixed value and depends on the number of ones or zeros of the preceding bit pattern of the information signal. Consequently, the following bit change is influenced by the common-mode voltage just before the change, which may give rise to bit-pattern-dependent signal distortion. Moreover, the fluctuating common-mode voltage may produce crosstalk to other sensitive circuits. These problems limit the bit rate of the information signal to be recorded.